MSR

Hardware prefetchers is a fundamental performance issue, RandomX accesses memory randomly, so prefetchers just don't work. All places where prefetching can help already have explicit prefetch instructions in the code. Sometimes prefetchers can be disabled in BIOS, for Intel it usually Hardware Prefetcher and Adjacent Cache Line Prefetch, but some prefetchers not possible disable even in BIOS.

Solution is configure prefetchers by using MSR registers from OS level.
If you use recent XMRig with root privileges (Linux) or admin privileges (Windows) the miner configure all MSR registers automatically.
If all good, the miner got all required privileges and your CPU supported you will saw line like below in miner log.

 msr  register values for "ryzen" preset has been set successfully (16 ms)

Supported CPUs:
  • Intel (Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell and newer)
  • Ryzen (All Zen based CPUs: Ryzen, Threadripper, EPYC)

XMRig revert initial MSR values on exit by default, anyway changes is not persistent, computer reboot always reset any changes.

Reddit discussions

Configuration

For configuration 2 options available in "randomx" object: "rdmsr" and "wrmsr"

rdmsr boolean

Use "rdmsr": false to disable reverting initial MSR values on exit.

wrmsr boolean/number/array

"wrmsr": false disable MSR feature.
"wrmsr": true (by default) enable MSR feature, this is identical to "wrmsr": 15 and "wrmsr": ["0x1a4:0xf"] for Intel or "wrmsr": ["0xc0011020:0x0", "0xc0011021:0x40:0xffffffffffffffdf", "0xc0011022:0x510000", "0xc001102b:0x1808cc16"] for Ryzen.

  • Default value 15 for Intel good in general, but may not best, please check issue #1433 on github for details.
  • For first generation Zen CPUs (with hardware bug) you can disable opcache and enable MSR mod by: "wrmsr": ["0xc0011020:0x0", "0xc0011021:0x60", "0xc0011022:0x510000", "0xc001102b:0x1808cc16"]

Manual OS configuration